Fern Nee Tan and Li Chuang Quek
Intel Microelectronics
This paper focuses on the power delivery network (PDN) characterization of high speed IC; particularly focusing on the on-die decoupling capacitance (Cdie) and on-die resistance and on die metal grid resistance (Rdie+Rgrid) characterization. For accurate modeling of Cdie, Rdie and Rgrid, two different measurements are studied by means of ‘On-chip’ and ‘On package’ measurement. As the ‘On package’ measurement approach’ is a known valid approach established and relied on for many years, it is used as a benchmark to guide us in the relatively new approach of ‘On chip’ in order to derive the right model for Cdie/Rdie/Rgrid. As both measurement setups are different, one as a direct on-chip measurement, while the other has an additional package substrate, the paper will describe a methodology to compensate the package parasitic from the model extracted; so that the final model is a standalone Cdie/Rdie/Rgrid model without the contribution of added parasitic from the package substrate. To ensure consistency, a wafer structure which consist only the power grid structure is measured and correlated with the power grid modeling tool to confirm that both modeling methodology and measurement methodology are correlated and accurate before applying the Rgrid model. The new method has shown a good correlation to the existing method to within 95% accuracy.