Negative Bias Temperature Instability (NBTI) and Positive Bias Temperature Instability (PBTI) occur when transistors are under negative bias. These effects which can increase the threshold voltage of transistors and decrease transistors speed have become a major problem to the circuit reliability. Retention registers are storage cells that are widely used in the power gating architecture. These registers can keep the current states in the always-on blocks of the retention registers. However, these registers also suffer from the significant NBTI and PBTI effects because the always-on block suffer from significant aging effects. This paper investigates the aging effect on various D-type retention registers. First, this paper analyzes the setup and hold time of retention registers under the NBTI and PBTI effects. Second, because the always-on circuit in power gating structure always suffers from NBTI and PBTI effects, the required time to store the data into an always-on circuit become higher from 0.6x~1.4x in 32nm technology. Thus, the paper analyzes the required time as well. Finally, this paper uses the selective transistor sizing technique to improve the setup, hold and required times of various D-type retention registers. Using 20%~90% selective transistor sizing can improve the setup and hold time from 8.1%~41.2%.