This paper analyzes the ability of an optimized via design to achieve higher channel bandwidth by minimizing impedance discontinuity of a high speed serial link above 5Gbps owing to the parasitic capacitive effect of a via on a single Printed Circuit Board (PCB). The methods of optimized via design are back-drilling plated through hole, removing unused pads and increasing anti-pad clearance. Different via features and their impact are studied in 3D model extraction using EMPro software from Agilent and simulations with Advanced Design System (ADS) where measurement of insertion loss, time domain reflectometry (TDR) and eye diagram are used. Subsequently, the simulation results are used to correlate with measurement results from a prototype PCB.