Asia Symposium on Quality Electronic Design (ASQED)

ASQED09 Tutorials

Tera-scale Computing and Interconnect Challenges – 3D Stacking Considerations

Tanay KarnikTanay Karnik

Principal Engineer

This presentation will introduce technology scaling trends and new challenges. We are at an I/O inflection point due to Tera-scale computing needs. The tutorial will describe the implication to I/O and memory bandwidth and present various options. 3D integration will be presented in detail with die/wafer stacking considerations. The tutorial outline is as follows:

  • Technology scaling trends
    • CMOS transistor scaling
    • Cache memory scaling
    • Projections
  • Tera-scale computing
    • Multi-core processor trends
    • High performance computing applications
    • Multi-core processor results
  • Implications to interconnects
    • Interconnect bandwidth
    • Memory bandwidth
  • Technology options
    • Multi-chip modules
    • System in a package or socket
  • 3D stacking considerations
    • Motivation
    • Advantages of 3D
    • Application to memory
    • 3D processing and assembly
    • Thermal consideration

About Tanay Karnik

Tanay Karnik (M'88, SM'04) received his Ph.D. in Computer Engineering from the University of Illinois at Urbana-Champaign in 1995. From 1995 to 1999, he worked in the Strategic CAD Lab at Intel. Since March 1999, he has lead the power delivery, soft error rate, and low power circuits research in the Circuits Research, Intel Labs, where he is Principal Engineer and manager of low power circuits research. His research interests are in the areas of variation tolerance, power delivery, soft errors and physical design. He has published over 40 technical papers, has 46 issued and 32 pending patents in these areas. He received an Intel Achievement Award for the pioneering work on integrated power delivery. He has presented several invited talks and tutorials, and has served on 5 PhD students' committees. He was a member of DAC, ICCAD, ICICDT and ISQED program committees and JSSC, TCAD, TVLSI, TCAS review committees. Tanay was General Chair of ISQED'08, ISQED’09 and ICICDT'08. Tanay is an ISQED Fellow.

Advanced Packaging Technologies and Future Interconnection Trends

Joseph Fjelstad Joseph Fjelstad
Verdant Electronics

IC packaging technology is the first interconnection element supporting the semiconductor chip, and today is the primary gatekeeper of electronic system performance and a critical technology for all future electronics, There are presently many packaging options available, each with its own benefits and risks, understanding the basics of IC packaging is vital to successful product design. This course reviews common IC packages, including chip scale, BGA, 3-D stacked and folded packages. A review of wafer-level packaging and emerging TSV technologies is also covered.

What you will learn:

  • Basic IC packaging roles and functions
  • Construction and manufacturing processes for common IC packages
  • Impact of IC package design on the assembly processes
  • What’s new, and where IC packaging technology is headed
  • Role of IC packaging technologies in electronics assembly
  • Chip scale packaging types and structures
  • Fundamental 3-D packaging concepts, structures and benefits
  • Reliability testing and electrical performance of chip scale packages (CSPs)
  • Impact of lead-free check points and alternative approaches
  • Standards and requirements for substrates
  • IC package testing requirements and strategies
  • The future of IC packaging and interconnection technology
  • Trends in the total integration of IC, package and PCB substrate (e.g., the Occam Process)
  • TSV (though silicon via technologies) and their structures

About Joseph Fjelstad

Joseph Fjelstad is the founder of Verdant Electronics and co-founder of SiliconPipe and was before that with Tessera, where he was appointed to the company's first fellowship. With more than 37 years of experience in the field of electronic interconnections, Fjelstad has been extremely active in sharing his acquired knowledge and has authored several books on the subject of electronic interconnections and packaging including "Chip Scale Packaging for Modern Electronics" and "Flexible Circuit Technology". Fjelstad is as well, a frequent contributor to numerous industry magazines and has written more than 300 magazine columns, articles and technical papers. He is as well a prolific inventor with more than 200 U.S. and international patents either issued or pending in the field of electronic interconnections. He is technical advisor to SMTA, a senior member of the IEEE, a member of the Jisso International Council and the International Electronics Interconnection Roadmap Committee. Fjelstad has received a number of awards including the IPC Presidents Award and was recognized in an industry poll as one the most influential persons in the electronics interconnection industry.