Asia Symposium on Quality Electronic Design (ASQED)

Keynotes at ISQED 2010

Tuesday, August 3

Creating a More Sustainable World through Smarter Design

John Chilton John Chilton
Senior Vice President, Marketing & Strategic Development

As more and more of the world relies on electronics - from mobile communications to medical advancements to electric cars - the drive to create faster, more complex and lower power designs is intense. This presents both challenges and opportunities. Every two years for almost six decades, our track record has demonstrated that the semiconductor industry can produce a new generation of chips that doubles chip performance all while becoming smaller, faster and cheaper. Now we, as an industry, face the challenge of producing "More than Moore" and addressing design issues at higher levels of abstraction at all points in the design process.

How do we continue to make high-quality technology accessible and extremely efficient? How do we capitalize on the rapidly growing demand for electronics in emerging markets while reducing overall power consumption? We all need to think bigger, think ecosystem, to successfully meet these technology and market demands now and in the future.

About John Chilton

John Chilton is responsible for all of Synopsys’ marketing functions, including Product Marketing, Solutions Marketing, Corporate Marketing, Corporate Development, Strategy and Planning. Prior to his current role, Mr. Chilton served as General Manager of Synopsys’ IP, Professional Services, and System Level Design Businesses. Prior to Synopsys, Mr. Chilton served as CEO of Arkos Design, which was acquired by Synopsys in 1995, and Datalogic/EMS, an early producer of RFID technology. Mr. Chilton holds a B.S.E.E. from UCLA and an M.S.E.E. from USC.

Neuromorphics: The reality of nanoscale devices as part of future System On System (SoS) Integration

Kamran Eshraghian Prof. Kamran Eshraghian
founder and President
Eshraghian Laboratories Pty Ltd (ELabs)

The evolution of System-on-Chip (SoC) and System-in-Package (SiP) introduce a 3rd dimension that can be described in terms of a “Volumetric Growth Law” that takes into account the multitechnology nature of integration for a future whereby Hyperintegration becomes the new domain for smart products. This new frontier is conjectured to move us way beyond Gordon Moore's 2-D scaling relationship as we begin to uncover new relationships and principles. While the future is becoming more difficult to predict, most likely we could anticipate an accelerating pace of change that span health sciences and intelligent health care, environmental management, smart energy management through to new innovations in man-machine interfaces, processing and communications. The presentation will highlight the inevitability of 3D Hyperintegration using technologies that are either in their infancy or those yet to be uncovered through initiatives of material physicists, computational chemists, and bioengineers such as spintronics, carbon nano tube field effect transistors, optical nanocircuits and metamaterials. The talk will focus upon one such technology - Memristor (Memory-Resistor) - the 4th basic electronic component conjectured to challenge the perspective and the mind-set that researchers and industry currently may have as to the reality of Terabit systems and the emergence of System on System (SoS) integration.

About Kamran Eshraghian

Prof. Kamran Eshraghian, founder and President of Eshraghian Laboratories Pty Ltd (ELabs). ELabs is a virtual platform for cutting-edge research into nano-based and micro-based technologies. He is best known in the international arena as the “grandfather” of CMOS VLSI Design. He has held faculty positions in Elelctronic Engineering and Computer Science in Australia, United States and Europe. A distinguished world expert in the field of VLSI systems and circuits, has held over 40 patents and co-authored 5 textbooks. His achievement is encapsulated in standard text “Principles of CMOS VLSI Design: A Systems Perspective”, used in over 800 universities through the world.

Bio-inspired Electronics based on Spin and Dipole Fluctuated System

Hitoshi Tabata Dr. Hitoshi Tabata
Professor, Head of Department of Bioengineering
The University of Tokyo

In this presentation, a new-type electronics (Biotronics) which is learned and derived from bio fluctuation will be discussed. As one of examples of controllable physical fluctuation system, the fabrication involves artificial superlattices and/or quantum wells of spin and dipole frustrated materials.

This is based on new physical properties coming from the co-existence of competed phases and “Yuragi” (fluctuation system). The development is that the flexible and adaptable information system and devices will originated from bio-inspired system. The academic discipline of new type of devices will be constructed and presented.

About Hitoshi Tabata

Dr. Hitoshi Tabata, Professor, Head of Department of Bioengineering, The University of Tokyo. The keynote highlights the creation of a new-type electronics known as biotronics) is learned from bio fluctuations. An example is a controllable physical fluctuation system. He received a Japan Society for the Promotion of Science(JSPS) Prize in 2008. His current research is in the area of “Nano-Bioelectronics”, “Artificial superlattices of functional oxides” and “Spin electronics and multi ferrotronics”. He is a member of Material Research Society, and Japan Society of Applied Physics.

Wednesday, August 4

Analog IC Market Trends: The OLD becomes NEW again

Paul Emerson Paul Emerson
General Manager New Business Proving Grounds, HVAL
Texas Instruments

In the past, the electronics industry has developed solutions for digital information creation, transmission and storage which allow countries, companies, and individuals to connect and share data in many new ways. With this infrastructure in place, electronics innovators are applying current technology to age old problems. Health, safety, energy, motion control and other major challenges will benefit dramatically.

Market trends, which consider both “old” and “new” industries, will be presented to highlight areas that governments, corporations, and individuals will focus their time and investments in the years to come. Analog IC design methodologies, process technologies, and development trends will be presented to show how industrial leaders will realize their next generation innovative analog IC products.

About Paul Emerson

As HVAL’s New Business Proving Grounds general manager, Paul Emerson is an experienced analog design engineer and business leader, with a thorough understanding of HVAL customers and business. Paul started his TI career in 1996 in the Storage Products Group (SPG) and advanced from design engineer to product line manager within the Preamp group, and then manager leading the overall SPG organization. Paul was elected to the TI Technical Ladder as Member, Group Technical Staff (MGTS) in 1999, and as Senior Member, Technical Staff (SMTS) in 2003. He is the inventor or co-inventor of 7 patents in Preamp circuit design. He earned his Bachelors of Electrical Engineering (BEE) and Masters of Science in Electrical Engineering (MSEE) from The Georgia Institute of Technology.

Leveraging parallel processing in SoCs

Jeroen Leitgen Dr. Jeroen Leijten
Co-Founder and Chief Technology Officer
Silicon Hive

To achieve a high level of computational efficiency in programmable processors two key measures must be taken. First, processors should focus on computing in parallel at modest clock rates. And second, control hardware overhead in processors should be minimized. C-programmable processors must combine multiple styles of parallelism and exhibit minimal control hardware overhead, all rightfully balanced towards the targeted application domain. Parallelism in computation must be matched with properly dimensioned parallelism in storage and I/O bandwidth. This means that rather than focus on a one-fits-all solution for different application domains, different programmable solutions must be tuned to different application domains to achieve the best possible balance between flexibility, performance, area and power for each domain.

This keynote speech will discuss the challenges and commercially proven solutions to achieve the above, using Silicon Hive technology as an example. Underlying all Silicon Hive solutions is the same basic processor architecture template and associated re-targetable software development tool suite. Key to achieving efficiency and guaranteeing quality, are powerful processor specification, exploration, and generation technology as well as ground-breaking software compilation technology. These technologies were developed as one integrated whole, based on decades of research and development combining vast expertise in processor architecture, compilation technology, application knowledge, and hardware design. Because of this integrated approach, Silicon Hive is able to take scalability in parallelism far beyond established limits. The keynote speech will address the key elements of this integrated approach in more detail.

About Jeroen Leijten

Jeroen has 15 years experience in parallel computer architectures and reconfigurable computing. At Silicon Hive he has been leading the development of Silicon Hive's parallel processing technology and related processor generation tools and libraries. At present he is responsible for all world-wide research and development within Silicon Hive. Prior to co-founding Silicon Hive, he was leading a next-generation processor architecture and software compiler codesign project in Philips Research. Within Philips Research he has worked as a senior scientist within research groups focussing on digital VLSI and systems on silicon. In 1998 he obtained a Ph.D. degree in reconfigurable multiprocessor architectures for real-time digital signal processing applications from the Eindhoven University of Technology. Jeroen currently holds more than 10 US patents on processor architecture and related technology.