This tutorial presents a technology focused over-view on 3D developments from the perspective of French public research. The notion of a generic technology toolbox, from which to pick and choose integration schemas will be presented. Different approaches to 3D technology integration will also be presented; notably 3D (and 2.5D) interposer technologies, 3D-IC technologies and heterogeneous integration (TSV-less) technologies.
• Development of 3D tool box
• Interposer approach
• 3D-IC approach
• Heterogeneous approach
About Mark Scannell
Mark SCANNELL has an engineering degree from National University Ireland. He has over 20 years experience in the electronics and semiconductor industry. He has worked for the one of the world’s leading semiconductor equipment suppliers in various engineering positions and as a technology business director. Mark has lived in several countries; notably Japan, Germany, USA and France. He has worked at CEA - Léti since 2005. Mark’s current position is Program Director for 3D Integration where his responsibilities include business development, patent portfolio management, public partnerships, industrial contracts and technology road mapping.
IC packaging has evolved from a simple, primarily mechanically oriented design task, to a very challenging, primarily electrically oriented design task. Flip-chips and routable package substrates introduced a new set of design challenges. C4 bumps, RDL routing and package level interconnect (including vias) added a tremendous amount of additional complexity to the off-chip interconnect path. Looking beyond the physical design challenges, I/O are getting faster and faster, meaning designers now had to pay more attention to off-chip signal integrity and power delivery. Package optimization, design and modeling became much more difficult. Modern 3D packaging technologies are now broadening package design challenges by introducing a new set of off-chip interfaces, including TSV interconnect, micro-bumps and silicon interposers. Managing this extremely complex off-chip interconnect path is one thing. Optimizing this interconnect path for routability, signal integrity and power delivery is where the real challenge lies. This tutorial will discuss the challenges involved with defining and developing a complete chip, package, board co-design methodology to support modern 3D packaging technologies.
About John Park
John Park brings 30 years of EDA design tool experience to his role as Methodology Architect for the System Design Division at Mentor Graphics. In this role, he is focused on defining solutions and methodologies for IC, Package & PCB co-development with an emphasis on advanced IC Packaging technologies. John has published multiple articles covering advanced IC packaging and co-design technologies. Prior to joining Mentor Graphics, John spent 19 years at Cadence Design Systems in various technical roles, defining and supporting tools and methodologies for IC P&R, Package substrate design and modeling as well as PCB layout.
Traditionally, memory performance has increased at a slower pace than that of CPUs, GPUs and ASICs. Besides increasing frequency, doubling and quadrupling of data transfer per clock signal (DDR and QDR) have increased data throughput, which have put tighter design constraints on both memory packaging and system design. To further increase the bandwidth while maintaining current system design, multiple channels per CPU have been implemented. Though these have addressed performance issues related to desktop systems, rapid change in system form-factors away from desktops, such as mobile (phones, tablets) and cloud computing (search, social, media) have added new challenges but also have provided new opportunities. The new challenges include miniaturization including multi-chip packaging, low power solutions for both mobile and data-center applications, and high capacity while delivering high performance. In this presentation, details regarding package level reliability and performance will be presented. The limitations of current system designs will be shown. Two example applications, mobile and data-centers, will be addressed and memory packaging approaches will be discussed. The challenges of wide IO for mobile memory will be covered in terms of packaging configurations and their trade-offs. For the data-center applications, multi-chip packaging and their implementation in conventional systems and possible new configurations will be presented.
About Ilyas Mohammed
Ilyas Mohammed is Senior Director and Principal Technologist at Tessera. His current work is in the area of Advanced Technologies, where he leads the efforts on creating and developing intellectual property covering the broad area of semiconductors, including computing, LEDs, MEMs, flexible electronics, etc. He works on identifying future technological challenges and creating solutions through innovation and research. Previously, he was the Director of Packaging Development at Tessera, where he worked on developing solutions in the areas of wafer level, 3D and flip-chip packaging. He has numerous publications and more than 30 issued and pending patents. He has an undergraduate degree from Indian Institute of Technology, Madras, and Ph.D. from the University of Texas, Austin in Aerospace Engineering and Engineering Mechanics.
As the semiconductor industry migrates toward extreme monolithic foundry level 3D heterogeneous structures for mixed-signal components and systems, 3D silicon/glass interposer and through silicon via (TSV) technology will play a significant role in next generation 3D packaging solutions. It is ubiquitous that 3D integration technologies are well suited to realize high density and high performance heterogeneous systems. 3D integration technologies rely on TSV technology, wafer thinning/handling technology and micro-bump technology. This presentation provides the fundamentals and individual skill sets mandatory for 3D integration technologies. In particular, wafer thinning and bonding , silicon/glass interposer design rules and supply chain, application specific silicon/glass interposer selection guideline, TSV manufacturing and thermal stress effect, signal-power integrity, test and verification, cost analysis for 3D processes and EDA tool perspective will be presented.
About Farhang Yazdani
Farhang Yazdani is the President and Chief Technical Officer of BroadPak Corporation. With over 17 years of experience in semiconductor packaging industry, he is widely regarded as an expert on 3D packaging technologies. Previously, he served in various management, technical and advisory positions with leading semiconductor companies worldwide. He has numerous publications and US patents issued and pending in the area of Packaging and Assembly, serves on various technical committees and is a frequent reviewer for IEEE Journal of Advanced Packaging. He has undergraduate and graduate degrees in Chemical Engineering and Mechanical Engineering from the University of Washington, Seattle. He is a member of AICHE, ASME, IEEE, IMPS, SPE and the Society of Rheology.