Asia Symposium on Quality Electronic Design (ASQED)

Tutorials at ASQED 2013

Manufacturing, Design, and Test of 2.5D- and 3D-Stacked ICs

Paul D. Franzon Paul D. Franzon
Alumni Distinguished Professor of Electrical and Computer Engineering

Three dimensional chips stacked using Through Silicon Via (TSV) technology has been under consideration and the subject of intensive research for several years now. Soon the technologies will become available through standard fabs. Will the technology be an instant hit, a niche, or a flop? What is needed to ensure it reaches hit status? What are the basic manufacturing steps and flows? This tutorial will discuss these question mainly in the context of the opportunities and challenges that face the designer. What are the significant opportunities presented by 3DIC? What problems will the designer face that will need clever solutions? What are the potential solution paths?

About Paul D. Franzon

Paul D. Franzon is currently a Distinguished Alumni Professor of Electrical and Computer Engineering at North Carolina State University. He earned his Ph.D. from the University of Adelaide, Adelaide, Australia in 1988. He has also worked at AT&T Bell Laboratories, DSTO Australia, Australia Telecom and two companies he cofounded, Communica and LightSpin Technologies. His current interests center on the technology and design of complex microsystems incorporating VLSI, MEMS, advanced packaging and nano-electronics. He has lead several major efforts and published over 200 papers in these areas. In 1993 he received an NSF Young Investigators Award, in 2001 was selected to join the NCSU Academy of Outstanding Teachers, in 2003, selected as a Distinguished Alumni Professor, and received the Alcoa Research Award in 2005. He served with the Australian Army Reserve for 13 years as an Infantry Solider and Officer. He is a Fellow of the IEEE.

Embedded System Design with Altera's Qsys

Saeid Nooshabadi  Saeid Nooshabadi
Professor of Computer Systems Engineering
Michigan Technological University

Embedded systems design is a hot application field which merges logic design and processor-based hardware development in a single or few chips solution. In recent years, embedded applications have emerged at a faster rate and used in every field of one can think of ranging from household products such as microwaves, to automotive products such as air bags sensing and control, to industrial robots which employ distributed processing and coordination. Various technologies have been used in the development of embedded systems; microcontroller, DSP processor, ASIC, and now FPGA. Embedded systems development involves hardware and software components development as they coexist in such systems. This tutorial presents an introduction to Altera's Qsys embedded system integration tool, which is used to design embedded digital hardware systems that contain components such as processors, memories, input/output interfaces, timers, and the like. The Qsys tool allows a designer to choose the components that are desired in the system by selecting these components in a graphical user interface. It then automatically generates the hardware system that connects all of the components together.

About Saeid Nooshabadi

Saeid Nooshabadi is the professor of Computer Systems Engineering, having a joint appointment, with Departments of Electrical & Computer Engineering, and Computer Science, Michigan Technological University, Michigan. Prior to his current appointment he has held multiple academic and research positions. His last two appointments were with the Gwangju Institute of Science and Technology, Republic of Korea (2007 to 2010), and with the University of New South Wales, Sydney, Australia (2000 to 2007). His research interests include VLSI information processing and low-power embedded processors for wireless applications.

SystemVerilog Verification using UVM 1.1

Jonathan Cheah Jonathan Cheah
Applications Consultant

In this tutorial, we will look at Object Oriented concepts in SystemVerilog and how the UVM framework utilizes it to provide a higher level of abstraction for verification. This abstraction to transaction level modelling allows the verification engineer to take on more complex designs, fitting perfectly for SOCs. You will learn how to develop a UVM explicitly-phased SystemVerilog test environment structure which can implement a number of different test cases with minimal modification. Within this UVM environment structure, you will develop stimulus factories, check and coverage callbacks, message loggers, transactor managers, and data flow managers

About Jonathan Cheah

Jonathan is a Synopsys Application Consultant specializing in the VCS simulator tool and is responsible for providing consultation, training and support management for various design teams since joining the company in 2009. Prior to Synopsys he was the first hire for the IP department of Altera Penang responsible for writing and verifying RTL; building SOCs targeting FPGA platforms; writing software models for the system builder tool and Hardware Abstraction Layer (HAL) for the IPs; qualified a new development kit and developed the SOFT IP examples; including managing test regressions and optimizing generation of high level view of the regression health. He was also the sole trainer for Altera Penang's University Program, developing syllabus and training lecturers from local institutions of higher learning to adopt the Quartus tool and incorporating the donated Apex Development Kits into the course structure. After which, he pioneered the adoption of HAPS FPGA debug platform for USB 2.0 in Marvell Penang which allows at-speed testing of the PHY. Additionally he was part of a 2-man team providing IT support for the design team, involving in tool installation, machine and storage solutions. Jonathan graduated from Universiti Teknologi Malaysia with B.Eng (Hons) in 2005.

UPF for Lower Power Design: An overview

Yeong Kig-Ling Yeong Kig-Ling
Applications Consultant

This tutorial will cover the current challenges and trends in low power designs. We will highlight common techniques that are ubiquitous in modern chip designs, as well as other advanced low power techniques used by some companies. We will then move on to introduce UPF and the role it plays in helping designers to implement these advanced techniques. Finally, we will go through an example of implementing a design with UPF.

About Yeong Kig-Ling

Yeong Kig-Ling has 10+ years of design experience. Starting his career in Intel Penang in 2002. He joined Synopsys in 2008 as a senior application consultant and has been working with customers to ensure successful design tapeout ever since. His professional experience and area of expertise is in Netlist to GDS supporting IC Compiler, the Synopsys place and route tool. He has also supported and worked with a few other customers to successfully migrate them to the UPF low power flow. Kig Ling graduated with an honors degree from University Sains Malaysia.

Taking Hardware-assisted verification to the next Level

Chee-Chun Tay Chee-Chun Tay
Applications Consultant
Mentor Graphics

Chip and verification complexities continue to grow. Despite these growing complexities, time-to-market pressures require that chip verification be completed on schedule. Hardware-assisted verification is used primarily to reduce risk by running more verification in a given time. Successfully completing this type of verification depends on three main parameters: performance of the verification engine; quickly adopting the changes in RTL, IP, or peripheral interfaces; and emulating the behaviour of the target environment. Ease-of-use, synergy with existing verification environments, and interoperability with software simulators are also contributing factors to successful hardware-assisted verification. This tutorial attempts to explore the industry's highly optimized emulation SoC technology. Its unique architecture gives users the flexibility to build highly productive verification environments through the implementation of a hardware stimulus, a software stimulus, or a combination of the two.

About Chee-Chun Tay

Chee-Chun Tay is AE consultant from the PacRim Regional Field Technical team with over 12 years of experiences in the semiconductor industry. His field of knowledge spans from DFT to Functional Verification and spearheads deployment efforts to address key customer's challenges in those areas. Prior to his current role, he was instrumental in the design, verification and test integration of the first generation ASIC and FPGA for 3G mobile transceiver base station technology successfully deployed in Japan. Chee-Chun received his BEng at Nanyang Technological University and a MSc degree at National University of Singapore.